Compact Software Implementation of AES on Atomic Smartphones Architecture
نویسندگان
چکیده
The smartphones have enhanced the way of life of present day generation in terms of businesses, communications, Internet browsing and so on. The hardware architecture of smartphones is becoming compact year by year due to reduction in the number of gates used, latency cycles and data paths. However, security plays a major role in order to enjoy optimally the functionalities of smartphones. This study therefore design and implement a compact software using AES-128 bit. Existing AES attacks based on records were studied and guided the application development. The work was evaluated in terms of encryption time, decryption time and throughput. The results were recorded and compared with earlier results. Our results are found to be faster and can be used to provide enhanced security on smartphones using cloud.
منابع مشابه
Implementing GCM on ARMv8
The Galois/Counter Mode is an authenticated encryption scheme which is included in protocols such as TLS and IPSec. Its implementation requires multiplication over a binary finite field, an operation which is costly to implement in software. Recent processors have included instructions aimed to speed up binary polynomial multiplication, an operation which can be used to implement binary field m...
متن کاملAtomic-AES v 2.0
Very recently, the Atomic AES architecture that provides dual functionality of the AES encryption and decryption module was proposed. It was surprisingly compact and occupied only around 2605 GE of silicon area and took 226 cycles for both the encryption and decryption operations. In this work we further optimize the above architecture to provide the dual encryption/decryption functionality in ...
متن کاملFPGA Can be Implemented Using Advanced Encryption Standard Algorithm
This paper mainly focused on implementation of AES encryption and decryption standard AES-128. All the transformations of both Encryption and Decryption are simulated using an iterativedesign approach in order to minimize the hardware consumption. This method can make it avery low-complex architecture, especially in saving the hardware resource in implementing theAES InverseSub Bytes module and...
متن کاملVery Compact FPGA Implementation of the AES Algorithm
In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key schedule are all implemented using small resources of only 222 Slices and 3 Block RAMs. This implementation easily fits in a low-cost Xilinx Spartan II XC2S30 FPGA. This implementation can encrypt and decrypt data streams of 15...
متن کاملA compact AES core with on-line error-detection for FPGA applications with modest hardware resources
This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expa...
متن کامل